This invention relates generally to electronic circuits carried on substrates of semiconductor materials and relates specifically to an input circuit used in such integrated circuits.
Integrated circuits comprise a substrate of semiconductor material that is processed to form electronic components in the top layers of the semiconductor material and with leads extending between the electronic components for desired interconnection. Interconnection to the integrated circuit is by way of wires attached to bonding pads carried on the substrate at the margin of the substrate. Electrical leads extending from the electronic components to these bonding pads to complete the circuits. These bonding pads occur at the periphery of the substrate.
As the area of the top surface of the integrated circuit increases and as designers try to make each integrated circuit directly compatible with more than one package option, a problem arises in that bonding pads can be displaced quite far from the input circuitry where these signals are used. This can create problems relating to electrical noise immunity, signal rise and fall times, nonuniformity of timing of received input signals and added capacitance at the bond pad.
In some cases, this problem has been attempted to be corrected by extending a metal or polysilicon connection from the bonding pad to the internal circuit where the signal is used. This arrangement becomes susceptible to noise due to the length of the metal or polysilicon lines because the TTL (transistor-transistor logic) signal traveling on this connection or lead can be bounced around by capacitive coupling from the substrate which lies directly underneath this line or from any other signal line located close to this line. This can cause an input stage or buffer to misread the logic level of the TTL level signal especially since the input stage typically is a CMOS stage trying to decipher the sometimes smaller voltages of a TTL level signal.
Regarding signal speed, since the signal traveling on the extended metal or polysilicon lead is at TTL voltages, the time for this signal to propagate to the input stage and then be detected can be considerably longer than if the signal was at CMOS logic levels. This can occur for TTL levels where the switching point may be a high percentage, such as 95%, of the entire transition of the received signal due to process variations when the circuit is being fabricated that can significantly raise or lower the trigger point. Faster recognition of the change in logic level signals would occur for CMOS logic levels where the transition would be approximately only 50% of the total transition, therefore requiring only 50% of the transition time. This stands as one good reason for not running TTL level signals long distances in CMOS logic circuitry.
Another problem is nonuniformity in signal timing. Different pads become located at different positions at the peripheral margin of the chip and, in the case of addresses, the input signals from these pads must all go to approximately the same location. These differences in propagation delays due to the difference in lead lengths causes non-uniformity in the times at which the address signals reach their input circuits. This becomes an undesirable situation that can greatly affect the set up and hold times of the address signals, which ideally, should be uniform. In particular this problem occurred on a 256K NMOS dynamic RMA.
Extending the metal or polysilicon connection from the bonding pad to the input circuit adds to the parasitic capacitance of the pad. This undesirable situation slows the charging and discharging of the pad by the address signal and the propagation of that signal to the input circuit. It also adds capacitance to the load that external circuitry must drive when using the chip.
Another arrangement for avoiding these problems is to move the entire input circuit next to its related bonding pad. This overcomes some problems and causes others. If the input circuit requires several other signals to control it then all of these signals must run to this circuit which is now located next to the bond pad. This will slow these signals because of the extra parasitic resistance and capacitance caused by the extra length in the clock leads. The extension of these clock signals leads also consumes area of the substrate surface. In the case of address leads, several clock signal leads need to be extended to each of the address signal receiving bond pads.